rggen
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to control and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
- amba
- apb
- asic
- axi
- csr
- eda
- fpga
- ral
- register-descriptions
- rtl
- soc
- systemverilog
- uvm
- uvm-ral-model
- uvm-register-model
- verilog
- vhdl
- wiki-documents
- wishbone-bus
